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authorPratik Prajapati <pratikkumar.v.prajapati@intel.com>2017-08-23 17:37:43 -0700
committerAaron Durbin <adurbin@chromium.org>2017-08-25 18:24:33 +0000
commit9027e1ba2f23eb6b418f60f133da1730b7d989d3 (patch)
tree7d8c1c7a0bef6faead5be1dd76702b00ae02a0bf /src/soc/intel/cannonlake/chip.h
parent15943df29c31d581a160612ef1757e7d24729dd7 (diff)
soc/intel/cannonlake: Init UPD params based on config
Initialize UPD params based upon config Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21175 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
-rw-r--r--src/soc/intel/cannonlake/chip.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index ea9f7d762a..48305fe642 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -165,7 +165,7 @@ struct soc_intel_cannonlake_config {
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
} chipset_lockdown;
- uint8_t SkipMpInit;
+ uint8_t FspSkipMpInit;
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced */