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authorFelix Singer <felixsinger@posteo.net>2020-12-20 19:44:18 +0000
committerPatrick Georgi <pgeorgi@google.com>2021-01-11 17:23:53 +0000
commitd456f65056530faccca31b392ffaff7bcc0953b3 (patch)
tree0528a0b95cd7ac09e28ea2ecd208f2f086255d3b /src/soc/intel/cannonlake/chip.h
parent5569bddf66b44caf88acb54ea4a5dc7c1286762a (diff)
{soc,vc,mb}/intel: Drop support for Cannon Lake SoC
Drop the support for the Intel Cannon Lake SoC for various reasons: * Most people can't use coreboot on Cannon Lake, since the required FSP binaries aren't publicly available. Given that FSP binaries for several newer platforms have been released, it's very unlikely that Cannon Lake FSP will ever be released. * It seems there is no interest in this, since the reference mainboard is the only available mainboard in tree. Also, remove the related reference mainboard intel/cannonlake_rvp and its FSP headers in intel/fsp2_0/cannonlake. Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
-rw-r--r--src/soc/intel/cannonlake/chip.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2727aa22a7..15592d54fa 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -89,9 +89,6 @@ struct soc_intel_cannonlake_config {
enum {
SaGv_Disabled,
SaGv_FixedLow,
-#if !CONFIG(SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS)
- SaGv_FixedMid,
-#endif
SaGv_FixedHigh,
SaGv_Enabled,
} SaGv;