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authorpraveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>2018-09-27 00:00:13 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-10-17 12:16:47 +0000
commit521e48c87da6c70644a03c7b5e77856a8e556e53 (patch)
tree67db1fc9a1a1748f8977756d6138f4489ee7ab4d /src/soc/intel/cannonlake/chip.h
parente26c4a461132087930e7137043ab6ada1b4147c7 (diff)
soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities. - Add gpio pin definitions for CNP-H and related changes. - Add gpio device name, host software ownership reg offset for CNP-H. BUG: none TEST: build and flash, boot to windows and yocto os on both CFL RVP8 & RVP11 and verify power management, IO device functionalities work fine. Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
-rw-r--r--src/soc/intel/cannonlake/chip.h8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index ca021c2b7d..74cb833bf6 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -24,12 +24,18 @@
#include <stdint.h>
#include <soc/gpio.h>
#include <soc/pch.h>
-#include <soc/gpio_defs.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
#include <soc/vr_config.h>
+#if IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#include <soc/gpio_defs_cnp_h.h>
+#else
+#include <soc/gpio_defs.h>
+#endif
+
+
struct soc_intel_cannonlake_config {