diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-02-02 13:32:49 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-03-16 22:48:06 +0000 |
| commit | 41483c9dff9bd68b4c67b947c4cd7175951b9723 (patch) | |
| tree | aec170fe3513fdd2156309be0eced2ed59617e7d /src/soc/intel/cannonlake/chip.h | |
| parent | ebd8a4f90cf58cd03a95fcc01acea1c59b0cad4e (diff) | |
soc/intel/cannonlake: Add required FSP UPD changes for CML
This patch adds required FSP UPD changes for CometLake SoC.
Also this patch tries to create common parse logic for CometLake as
well as cannonlake SOC.
We parse device tree parameters for PCI devices and fill values in FSP
UPDs. We fill UPDs based on pci device config as well as SerialIoDev
config of devicetree.
For PCI devices, if PCI device is disabled from devicetree, we'll assign
disable value to FSP UPD.
In case devicetree doesn't fill this parameter or value is invalid in
SerialIoDev config, default mode will be set to PCI.
In case of valid value, we'll fill the same value into FSP UPD.
BUG=none
BRANCH=none
TEST=check if CML board boots and proper UPD values are filled.
Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3e4bafc322..b4d78f3cda 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +36,8 @@ #include <soc/gpio_defs.h> #endif +#define SOC_INTEL_CML_UART_DEV_MAX 3 + struct soc_intel_cannonlake_config { /* Common struct containing soc config data required by common code */ @@ -101,7 +103,7 @@ struct soc_intel_cannonlake_config { * For CNL, options are as following * When enabled, memory will be training at three different frequencies. * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled - * For WHL/CFL options are as following + * For WHL/CFL/CML options are as following * When enabled, memory will be training at two different frequencies. * 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/ enum { @@ -308,10 +310,30 @@ struct soc_intel_cannonlake_config { * PchSerialIoIndexUART2 * * Mode select: + * For Cannonlake PCH following values are supported: + * PchSerialIoNotInitialized * PchSerialIoDisabled * PchSerialIoPci * PchSerialIoAcpi * PchSerialIoHidden + * PchSerialIoMax + * + * For Cometlake following values are supported: + * PchSerialIoNotInitialized + * PchSerialIoDisabled, + * PchSerialIoPci, + * PchSerialIoHidden, + * PchSerialIoLegacyUart, + * PchSerialIoSkipInit, + * PchSerialIoMax + * + * NOTE: + * PchSerialIoNotInitialized is not an option provided by FSP, this + * option is default selected in case devicetree doesn't fill this param + * In case PchSerialIoNotInitialized is selected or an invalid value is + * provided from devicetree, coreboot will configure device into PCI + * mode by default. + * */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; |