diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-29 17:25:46 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2017-08-30 15:45:14 +0000 |
| commit | 2678cd693a766f722e67c7d650a95e1d4a9af404 (patch) | |
| tree | 5726ceee236bc4baddaf5e170133ea35cb18d613 /src/soc/intel/cannonlake/chip.h | |
| parent | f10c8f9cf3930db624955f04cb6434d69e16030e (diff) | |
soc/intel/cannonlake: Add PrmrrSize and C6DRAM config
This patch ensures coreboot can set PRMRR size and C6DRAM
enable FSP-M UPDs.
Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.h')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 48305fe642..0ed41fc824 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -186,6 +186,14 @@ struct soc_intel_cannonlake_config { /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; + /* Enable C6 DRAM */ + uint8_t enable_c6dram; + /* + * PRMRR size setting with below options + * 0x00100000 - 1MiB + * 0x02000000 - 32MiB and beyond + */ + uint32_t PrmrrSize; }; typedef struct soc_intel_cannonlake_config config_t; |