diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-05-15 21:23:18 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-20 14:50:16 +0000 |
| commit | 76a8f9e29f3cb6aa2e971957eec7fc05abaf50b8 (patch) | |
| tree | cd1c89bb0a29d00daef14dcc9418f5931eeac128 /src/soc/intel/cannonlake/chip.c | |
| parent | dd5fa024260bf6fd19c077d640c34e27b742115b (diff) | |
soc/intel/cannonlake: Make use of gpio_pm_configure()
Provide option in chip.h to set dynamic local clock gating
setting.
BUG=b:130764684
TEST=Able to build and boot CML.
Change-Id: Iec60076398b745e11d5025e4d7a5c35374d918a4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/chip.c')
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 1bd34c34e0..faddbd5a24 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -166,6 +166,27 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) gpio_configure_pads(cfg, num_pads); } +/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */ +static void soc_fill_gpio_pm_configuration(void) +{ + uint8_t value[TOTAL_GPIO_COMM]; + const struct device *dev; + dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0); + if (!dev || !dev->chip_info) + return; + + const config_t *config = dev->chip_info; + + if (config->gpio_override_pm) + memcpy(value, config->gpio_pm, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + else + memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) * + TOTAL_GPIO_COMM); + + gpio_pm_configure(value, TOTAL_GPIO_COMM); +} + void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -176,6 +197,8 @@ void soc_init_pre_device(void *chip_info) /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ cnl_configure_pads(NULL, 0); + + soc_fill_gpio_pm_configuration(); } static void pci_domain_set_resources(struct device *dev) |