diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-28 13:56:24 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-03 11:26:41 +0000 |
| commit | 73b1bd7992fb33f33c33747fd0919fc495c3d5c4 (patch) | |
| tree | 26f50ea0b5d47777e877210e03c85a22af64c4d9 /src/soc/intel/cannonlake/bootblock | |
| parent | 91e7fe7b547396857c7165a2c68aad5fda8730e4 (diff) | |
soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
This patch performs below operations:
1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration
2. Move soc_gpio_pm_configuration() to gpio_common.c
3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration
is updated with devicetree.cb value even with platform reset.
BUG=b:144002424
TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb
Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/bootblock')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 39433a26d9..9ad7e86178 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -28,6 +28,7 @@ #include <intelblocks/smbus.h> #include <intelblocks/tco.h> #include <soc/bootblock.h> +#include <soc/gpio.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/p2sb.h> @@ -198,4 +199,7 @@ void pch_early_init(void) pmc_gpe_init(); enable_rtc_upper_bank(); + + /* GPIO community PM configuration */ + soc_gpio_pm_configuration(); } |