diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2017-06-05 13:22:24 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-13 19:28:27 +0000 |
| commit | 3e2e0508c2f41242355dfbfe42b9e34adcb1a92a (patch) | |
| tree | 2b271acdb1a7f9afe3ff4a49cdd226c29914a320 /src/soc/intel/cannonlake/bootblock | |
| parent | 5b8987ae46512b5550d15fafd54b270ec913422d (diff) | |
soc/intel/cannonlake: Add early CPU initialization
Add basic CPU initialization for bootblock, as well as relevant headers.
Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/bootblock')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/cpu.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c new file mode 100644 index 0000000000..5b336da497 --- /dev/null +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/cpulib.h> +#include <intelblocks/fast_spi.h> +#include <soc/bootblock.h> + +void bootblock_cpu_init(void) +{ + /* Temporarily cache the memory-mapped boot media. */ + if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) && + IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH)) + fast_spi_cache_bios_region(); +} + |