diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-06-15 11:19:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-22 13:15:39 +0000 |
| commit | 5e8c906cabd37e74cda5f15d13a7fdd1db343ed0 (patch) | |
| tree | 7f3037a18968415d331be1da42a39a0a65341adc /src/soc/intel/cannonlake/bootblock | |
| parent | 481c52ddd5ea77fcf6767f358ae33246e91d63a8 (diff) | |
soc/intel/{apl,cnl}: Remove FSP CAR option
One of the reason FSP-T support had to be kept in place was for
Intel Bootguard. This now works with native CAR code, so there is no
reason to keep FSP-T as an option for these platforms.
APL did not even build with FSP_CAR and finding FSP-T using walkcbfs
was only recently fixed using FMAP, so there can be no doubt that this
option was never used with coreboot master.
Change-Id: I0d5844b5a6fd291a13e5f467f4fc682b17eafa63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake/bootblock')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/bootblock.c | 32 |
1 files changed, 0 insertions, 32 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 01329bf9b1..222193976a 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -12,38 +12,6 @@ #include <soc/iomap.h> #include <soc/pch.h> -#if CONFIG(FSP_CAR) -#include <FsptUpd.h> - -const FSPT_UPD temp_ram_init_params = { - .FspUpdHeader = { - .Signature = 0x545F4450554C4643ULL, /* 'CFLUPD_T' */ - .Revision = 1, - .Reserved = {0}, - }, - .FsptCoreUpd = { - /* - * It is a requirement for firmware to have Firmware Interface Table - * (FIT), which contains pointers to each microcode update. - * The microcode update is loaded for all logical processors before - * cpu reset vector. - * - * All SoC since Gen-4 has above mechanism in place to load microcode - * even before hitting CPU reset vector. Hence skipping FSP-T loading - * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. - * - * Note: CodeRegionSize must be smaller than or equal to 16MiB to not - * overlap with LAPIC or the CAR area at 0xfef00000. - */ - .MicrocodeRegionBase = 0, - .MicrocodeRegionSize = 0, - .CodeRegionBase = (uint32_t)0x100000000ULL - CACHE_ROM_SIZE, - .CodeRegionSize = (uint32_t)CACHE_ROM_SIZE, - }, -}; -#endif - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { /* Call lib/bootblock.c main */ |