diff options
| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2019-05-27 13:06:35 +0800 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-07-17 14:28:41 +0000 |
| commit | 38c3ff7b6ef2875b789d9621363db9165b9a1078 (patch) | |
| tree | f13e8f98cac2ae0e260e2100c94d4f60d1420109 /src/soc/intel/cannonlake/bootblock | |
| parent | f2ac0137566076262152f74b6b6761c9f6f2def2 (diff) | |
soc/intel/cannonlake: Add device Ids for new CFL SKUs support
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms
and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/cannonlake/bootblock')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/report_platform.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 1cbbd6384d..4bb06fb347 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -40,6 +40,8 @@ static struct { { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, + { CPUID_COFFEELAKE_P0, "Coffeelake P0" }, + { CPUID_COFFEELAKE_R0, "Coffeelake R0" }, { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, @@ -53,10 +55,13 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_ID_U, "Cannonlake-U" }, { PCI_DEVICE_ID_INTEL_CNL_ID_Y, "Cannonlake-Y" }, { PCI_DEVICE_ID_INTEL_CFL_ID_U, "Coffeelake U (4+3e)" }, - { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)" }, - { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)" }, + { PCI_DEVICE_ID_INTEL_WHL_ID_W_4, "Whiskeylake W (4+2)" }, + { PCI_DEVICE_ID_INTEL_WHL_ID_W_2, "Whiskeylake W (2+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_H_8, "Coffeelake-H (8+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_DT_8, "Coffeelake-S DT(8+2)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_S_WS_8, "Coffeelake-S WS(8+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_2_2, "CometLake-U (2+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, @@ -76,6 +81,7 @@ static struct { { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, "Cannonlake-H C246" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" }, @@ -101,7 +107,9 @@ static struct { { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_XEON_GT2, "Coffeelake-H Xeon GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_1, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2_3, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, |