diff options
| author | Felix Singer <felixsinger@posteo.net> | 2022-12-16 07:11:17 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2022-12-23 10:18:48 +0000 |
| commit | 35e65a8bc36628baad7d2ed94bef7619971e6d88 (patch) | |
| tree | a3b4d2afe3494eee4049db95f04a69d61113f006 /src/soc/intel/cannonlake/acpi | |
| parent | 86bc2e708dc2600c5611b6573d43645e7d57e561 (diff) | |
tree: Replace And(a,b,c) with ASL 2.0 syntax
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where
possible.
Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/scs.asl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index 5e8fb33f75..7def761f75 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -45,7 +45,7 @@ Scope (\_SB.PCI0) { ^^SCSC (PID_EMMC) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) + PMCR &= 0xFFFC ^TEMP = PMCR } @@ -209,7 +209,7 @@ Scope (\_SB.PCI0) { ^^SCSC (PID_SDX) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) + PMCR &= 0xFFFC ^TEMP = PMCR #if CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE) |