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authorMatt DeVillier <matt.devillier@gmail.com>2019-02-25 23:40:40 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-02-27 11:04:00 +0000
commitce529b631819574c3e1f6b10e60725df1638013e (patch)
tree72149507e54c8ff754936f9aa52e1bb7bd959593 /src/soc/intel/cannonlake/acpi
parent2201da3a8b9497792137bfa13cb47343efa5e42b (diff)
mb/google/cyan: fix RAM training on edgar variant
Adapted from Chromium commit 5351dc0d [Edgar: To set the RX ODT limit and dram geometry with RAMID detection] Several cyan variants require memory init parameters be passed to FSP for handling of specific Micron modules; without these, RAM init will fail when loading training data from the MRC cache, and boot will halt. This was missed when I upstreamed edgar along with the other cyan variants, so add the required memory init parameters for edgar as per its source Chromium branch. Test: build/boot on edgar board with affected Micron memory modules, verify boot successful with populated MRC cache. Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/31615 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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