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authorGuangjie Song <guangjie.song@mediatek.corp-partner.google.com>2024-07-24 16:45:19 +0800
committerYu-Ping Wu <yupingso@google.com>2024-11-08 07:37:29 +0000
commit946b2556f90df6adc220edb006b4dc03f6440f28 (patch)
tree5d1835703704df4ccbb19f991e2a1f694d7e090d /src/soc/intel/cannonlake/acpi
parent352d06451b24b8d9d99b07ebbb2b41af21a29607 (diff)
soc/mediatek/mt8196: Add PLL and clock init support
Add PLL and clock init code, frequency meter and APIs for raising little CPU frequency and set tvdpll frequency. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song@mediatek.corp-partner.google.com> Change-Id: Icac99fb210c87c8b7b14af627fbd2f14e4c47240 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi')
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