diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-09-25 14:33:17 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-03 20:24:35 +0000 |
| commit | 5d11cc9d7e0ee016d6b6c540d010b212291d61cd (patch) | |
| tree | 14c4b55ae277934b61d580c71f9917695ad4fdf0 /src/soc/intel/cannonlake/acpi/southbridge.asl | |
| parent | 747f05675ecf2d0fa4635c3b25e5726f7fe7d98d (diff) | |
soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
Add ACPI methods for gpio, scs and pcr.
TEST=Boot to OS.
Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 3d6538e200..408c31bfde 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -18,3 +18,12 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl" + +/* eMMC, SD Card */ +#include "scs.asl" + +/* PCR access */ +#include "pcr.asl" + +/* GPIO controller */ +#include "gpio.asl" |