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authorBora Guvendik <bora.guvendik@intel.com>2017-09-25 14:33:17 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-03 20:24:35 +0000
commit5d11cc9d7e0ee016d6b6c540d010b212291d61cd (patch)
tree14c4b55ae277934b61d580c71f9917695ad4fdf0 /src/soc/intel/cannonlake/acpi/scs.asl
parent747f05675ecf2d0fa4635c3b25e5726f7fe7d98d (diff)
soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
Add ACPI methods for gpio, scs and pcr. TEST=Boot to OS. Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/scs.asl')
-rw-r--r--src/soc/intel/cannonlake/acpi/scs.asl24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
new file mode 100644
index 0000000000..11564ae7d4
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0) {
+
+ /* SD CARD */
+ Device (SDXC)
+ {
+ Name (_ADR, 0x00140005)
+
+ } /* Device (SDXC) */
+}