diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2019-12-13 12:31:46 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-26 10:51:22 +0000 |
| commit | 086f0faf756a2d4e71fd9c1d27335af240418b19 (patch) | |
| tree | d80d93faf567f9cebfbdfe11742c9acd7afb3f58 /src/soc/intel/cannonlake/acpi/lpit.asl | |
| parent | a8ab2b33a41ac05899885608c6ca9fcd658859b6 (diff) | |
soc/intel/cannonlake: Move GPIO PM configuration to soc level
Enable GPIO clock gating when enter s0ix/Sx and save the PM bits.
Restore the PM bits when exit s0ix/Sx.
BUG=b:144002424
TEST=Check GPIO PM bits when enter/exit s0ix are expected
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/lpit.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/lpit.asl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 74d4fe6396..e0e23cac4e 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -16,6 +16,8 @@ External(\_SB.MS0X, MethodObj) External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) +External(\_SB.PCI0.EGPM, MethodObj) +External(\_SB.PCI0.RGPM, MethodObj) scope(\_SB) { @@ -73,6 +75,15 @@ scope(\_SB) If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X(1) } + + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } } /* * Function 6 - Low Power S0 Exit Notification @@ -87,6 +98,12 @@ scope(\_SB) If (CondRefOf (\_SB.MS0X)) { \_SB.MS0X(0) } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } } } Return(Buffer(One) {0x00}) |