diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-12-27 17:01:09 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-03 19:50:00 +0000 |
| commit | 5ff742c740c3d39df85596a99046ef88aef5351f (patch) | |
| tree | 9281c27d5e93f511e8269e29eb4fb2a50c24e29d /src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl | |
| parent | 334be3289d6ca16e806bd1e2aef87637cebb3122 (diff) | |
soc/intel/cannonlake: Add cannonlake ACPI GPIO op
Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to
implement GPIO toggling method, covered for both CNP_LP and CNP_H pch.
BUG=N/A
TEST=Build and boot up fine on sarien platform, add an dummy STSX in
DSDT table, read back from iotools to confirm the GPIO tx state get
updated.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f
Reviewed-on: https://review.coreboot.org/c/30461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl | 18 |
1 files changed, 1 insertions, 17 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl index e872b09dd0..acbd2ea430 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl @@ -15,7 +15,7 @@ #include <soc/gpio_defs_cnp_h.h> #include <soc/irq.h> #include <soc/pcr_ids.h> - +#include "gpio_op.asl" Device (GPIO) { @@ -107,19 +107,3 @@ Method (GADD, 1, NotSerialized) Add (Local2, PAD_CFG_BASE, Local2) Return (Add (Local2, Multiply (Local1, 16))) } - -/* - * Get GPIO Value - * Arg0 - GPIO Number - */ -Method (GRXS, 1, Serialized) -{ - OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) - Field (PREG, AnyAcc, NoLock, Preserve) - { - VAL0, 32 - } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) - - Return (Local0) -} |