diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-07 12:25:20 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-19 23:06:07 +0000 |
| commit | 0ade3133a0565df7b917a0f82869b10c3d4c57d4 (patch) | |
| tree | 4bf7a062009ba9bff96c97d4003124c8582f977c /src/soc/intel/cannonlake/Makefile.inc | |
| parent | e8253fea6308afd186bb349b8f5b831f7d2c9381 (diff) | |
soc/intel/cannonlake: Add minimal changes to call FSP Memoryinit
The following minimal changes are needed to make system boot until FSP
memoryinit got called.
1. Program SA BARs
2. Assume previous power state is S0.
Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 27c2e9b864..480e0477ad 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) +subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc |