diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-08-17 21:09:45 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-24 16:06:30 +0000 |
| commit | 01eda28bff233dbcb996ed697a7e28b7a01b597d (patch) | |
| tree | 99391d42b62b775f45e90a9f6444283284e1a3cf /src/soc/intel/cannonlake/Makefile.inc | |
| parent | 23e5ba9a733272562cc69b031055c6a7149cbabc (diff) | |
soc/intel/cannonlake: Add cpu.c and MP init support
Add initial MP init support. This boots up all CPUs.
Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 10d444be4b..435ce2d791 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -2,6 +2,8 @@ ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc @@ -25,6 +27,7 @@ romstage-y += spi.c romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-y += chip.c +ramstage-y += cpu.c ramstage-y += gspi.c ramstage-y += memmap.c ramstage-y += pmutil.c |