diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-14 11:09:10 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-15 20:21:31 +0000 |
| commit | 2f764f7dfe95e318057a241d8136fc866ebfed60 (patch) | |
| tree | 55510c6083a6cf4f650a748923ae1b1addc168f5 /src/soc/intel/cannonlake/Makefile.inc | |
| parent | 8465a81e81dfb2ed1fc24b9cf053b09d86fa5163 (diff) | |
soc/intel/cannonlake: Call into FSP siliconinit
The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
This patch was merged too early, and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20581
Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20687
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 9c2256f973..297d34f176 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -18,7 +18,8 @@ romstage-y += memmap.c romstage-y += reset.c romstage-$(CONFIG_UART_DEBUG) += uart.c -ramstage-y += cbmem.c +ramstage-y += chip.c +ramstage-y += memmap.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c |