diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-14 11:09:10 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-21 15:56:16 +0000 |
| commit | dbe7f893c0e3fffc4e9862d872d65df752feaf9d (patch) | |
| tree | 2d0d3e2fd4f7d5313026440a62208cb40428bcd0 /src/soc/intel/cannonlake/Makefile.inc | |
| parent | 399c022a8c6cba7ad6d75fdf377a690395877611 (diff) | |
soc/intel/cannonlake: Call into FSP siliconinit
The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index e427f98929..f166f1a3fc 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -16,7 +16,8 @@ romstage-y += cbmem.c romstage-y += reset.c romstage-$(CONFIG_UART_DEBUG) += uart.c -ramstage-y += cbmem.c +ramstage-y += chip.c +ramstage-y += memmap.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-$(CONFIG_UART_DEBUG) += uart.c |