diff options
author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-11 12:33:22 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-07-21 15:55:40 +0000 |
commit | 399c022a8c6cba7ad6d75fdf377a690395877611 (patch) | |
tree | 44a66a2fa6f7065e8c82289495b2df0e5065e972 /src/soc/intel/cannonlake/Makefile.inc | |
parent | 4cfae2f574c93c5640958fefa9f218c19e11399d (diff) |
soc/intel/cannonlake: Add postcar stage support
Initialize postcar frame once finish FSP memoryinit
Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Makefile.inc')
-rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 480e0477ad..e427f98929 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -5,20 +5,23 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc -bootblock-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c +bootblock-$(CONFIG_UART_DEBUG) += uart.c romstage-y += cbmem.c romstage-y += reset.c -romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c +romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-y += cbmem.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c -ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c +ramstage-$(CONFIG_UART_DEBUG) += uart.c + +postcar-y += memmap.c +postcar-$(CONFIG_UART_DEBUG) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake |