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| author | Matt DeVillier <matt.devillier@gmail.com> | 2023-10-21 20:57:39 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-10-26 18:01:29 +0000 |
| commit | 859a781705ae8347fe6ab4026917e8be6c3f4ccf (patch) | |
| tree | a014da222c428fb8b5a997cfeb4f3dfd19c4d6c0 /src/soc/intel/cannonlake/Kconfig | |
| parent | 1dd435c630518aac095a012114de2fe65df587c6 (diff) | |
soc/intel/cannonlake: Add/use chipset devicetrees
Change-Id: I8ceae832e60cd3094b4a34ab3a279e5a011f2c80
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fbee465743..92a99c43a3 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -9,6 +9,7 @@ config SOC_INTEL_CANNONLAKE_BASE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DISPLAY_FSP_VERSION_INFO + select DRIVERS_USB_ACPI select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP @@ -163,6 +164,11 @@ config FSP_TEMP_RAM_SIZE Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config CHIPSET_DEVICETREE + string + default "soc/intel/cannonlake/chipset_pch_h.cb" if SOC_INTEL_CANNONLAKE_PCH_H + default "soc/intel/cannonlake/chipset.cb" + config IFD_CHIPSET string default "cnl" |