diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-06-15 11:19:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-22 13:15:39 +0000 |
| commit | 5e8c906cabd37e74cda5f15d13a7fdd1db343ed0 (patch) | |
| tree | 7f3037a18968415d331be1da42a39a0a65341adc /src/soc/intel/cannonlake/Kconfig | |
| parent | 481c52ddd5ea77fcf6767f358ae33246e91d63a8 (diff) | |
soc/intel/{apl,cnl}: Remove FSP CAR option
One of the reason FSP-T support had to be kept in place was for
Intel Bootguard. This now works with native CAR code, so there is no
reason to keep FSP-T as an option for these platforms.
APL did not even build with FSP_CAR and finding FSP-T using walkcbfs
was only recently fixed using FMAP, so there can be no doubt that this
option was never used with coreboot master.
Change-Id: I0d5844b5a6fd291a13e5f467f4fc682b17eafa63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 29 |
1 files changed, 2 insertions, 27 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index aa5e5e9cca..dfb1be4879 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -57,12 +57,12 @@ config CPU_SPECIFIC_OPTIONS select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 - select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP select HAVE_FSP_LOGO_SUPPORT select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP @@ -80,6 +80,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI select SOC_INTEL_COMMON_BLOCK_CPU @@ -276,32 +277,6 @@ config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE This will enable a workaround in ASL _PS3 and _PS0 methods to force SD_PWR_ENABLE to stay low in D3. -choice - prompt "Cache-as-ram implementation" - default USE_CANNONLAKE_CAR_NEM_ENHANCED - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config USE_CANNONLAKE_CAR_NEM_ENHANCED - bool "Enhanced Non-evict mode" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED - help - A current limitation of NEM (Non-Evict mode) is that code and data - sizes are derived from the requirement to not write out any modified - cache line. With NEM, if there is no physical memory behind the - cached area, the modified data will be lost and NEM results will be - inconsistent. ENHANCED NEM guarantees that modified data is always - kept in cache while clean data is replaced. - -config USE_CANNONLAKE_FSP_CAR - bool "Use FSP CAR" - select FSP_CAR - help - Use FSP APIs to initialize and tear down the Cache-As-Ram. - -endchoice - config FSP_HEADER_PATH default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE_1 |