diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-08-16 22:18:52 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-21 20:37:57 +0000 |
| commit | b3dfcb863cdc62cd2cb65e97e0043311b151c558 (patch) | |
| tree | 1fbd8b130d79599f82212e719781d52f6b5e32c2 /src/soc/intel/cannonlake/Kconfig | |
| parent | 7a357eb8657fd891aad33fd710d2f9d4d80c9130 (diff) | |
soc/intel/cannonlake: Enable common PMC code for CNL
This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/cannonlake/Kconfig')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fb2ed69794..4267ba95d5 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -7,6 +7,7 @@ if SOC_INTEL_CANNONLAKE config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 @@ -34,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMBUS |