diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-25 00:32:44 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-14 08:37:52 +0000 |
| commit | d5689dd289d1108249d8c7ed779ae62fbd8963bf (patch) | |
| tree | 801c3ee516c6eeb3e4e70ac6fdbba6d6fdb9fb0f /src/soc/intel/broadwell | |
| parent | 2aaf7c0a1d1a895805772fe5f878606161c8d3c5 (diff) | |
soc/intel/broadwell/pcie.c: Add some null checks
These are present in Lynx Point.
Change-Id: I381f3cbf5fd18c952622f757135c0bde9ed6ed0d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45715
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 01ee06895f..0d41d42525 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -182,7 +182,7 @@ static void pch_pcie_device_set_func(int index, int pci_func) /* Determine the new devfn for this port */ new_devfn = PCI_DEVFN(PCH_DEV_SLOT_PCIE, pci_func); - if (dev->path.pci.devfn != new_devfn) { + if (dev && dev->path.pci.devfn != new_devfn) { printk(BIOS_DEBUG, "PCH: PCIe map %02x.%1x -> %02x.%1x\n", PCI_SLOT(dev->path.pci.devfn), @@ -204,6 +204,9 @@ static void pcie_enable_clock_gating(void) int rp; dev = rpc.ports[i]; + if (!dev) + continue; + rp = root_port_number(dev); if (!dev->enabled) { |