x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

10 files changed, 64 insertions, 62 deletions

diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 2a6dc1744a..41372158a0 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -58,7 +58,8 @@ static void adsp_init(struct device *dev)
 	 * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
 	 */
 	tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
-	write32(bar0->base + tmp32 + ADSP_SHIM_LTRC, ADSP_SHIM_LTRC_VALUE);
+	write32(res2mmio(bar0, tmp32 + ADSP_SHIM_LTRC, 0),
+		ADSP_SHIM_LTRC_VALUE);
 
 	/* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
 	pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
@@ -115,9 +116,9 @@ static void adsp_init(struct device *dev)
 				ADSP_PCICFGCTL_ACPIIE);
 
 		/* Put ADSP in D3hot */
-		tmp32 = read32(bar1->base + PCH_PCS);
+		tmp32 = read32(res2mmio(bar1, PCH_PCS, 0));
 		tmp32 |= PCH_PCS_PS_D3HOT;
-		write32(bar1->base + PCH_PCS, tmp32);
+		write32(res2mmio(bar1, PCH_PCS, 0), tmp32);
 	} else {
 		printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");
 
diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c
index 80caa2c2eb..76868059ec 100644
--- a/src/soc/intel/broadwell/hda.c
+++ b/src/soc/intel/broadwell/hda.c
@@ -36,7 +36,7 @@ u32 cim_verb_data_size = 0;
 const u32 * pc_beep_verbs = NULL;
 u32 pc_beep_verbs_size = 0;
 
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(u8 *base, u32 codec_mask)
 {
 	int i;
 
@@ -52,7 +52,7 @@ static void codecs_init(u32 base, u32 codec_mask)
 		hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
 }
 
-static void hda_pch_init(struct device *dev, u32 base)
+static void hda_pch_init(struct device *dev, u8 *base)
 {
 	u8 reg8;
 	u16 reg16;
@@ -108,7 +108,7 @@ static void hda_pch_init(struct device *dev, u32 base)
 
 static void hda_init(struct device *dev)
 {
-	u32 base;
+	u8 *base;
 	struct resource *res;
 	u32 codec_mask;
 	u32 reg32;
@@ -118,8 +118,8 @@ static void hda_init(struct device *dev)
 	if (!res)
 		return;
 
-	base = (u32)res->base;
-	printk(BIOS_DEBUG, "HDA: base = %08x\n", (u32)base);
+	base = res2mmio(res, 0, 0);
+	printk(BIOS_DEBUG, "HDA: base = %p\n", base);
 
 	/* Set Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 0f27fec625..31293e5ed3 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -246,14 +246,14 @@ static struct resource *gtt_res = NULL;
 static unsigned long gtt_read(unsigned long reg)
 {
 	u32 val;
-	val = read32(gtt_res->base + reg);
+	val = read32(res2mmio(gtt_res, reg, 0));
 	return val;
 
 }
 
 static void gtt_write(unsigned long reg, unsigned long data)
 {
-	write32(gtt_res->base + reg, data);
+	write32(res2mmio(gtt_res, reg, 0), data);
 }
 
 static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 394a9d7bdd..53cc4b8a24 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -53,22 +53,22 @@ static void pch_enable_ioapic(struct device *dev)
 {
 	u32 reg32;
 
-	set_ioapic_id(IO_APIC_ADDR, 0x02);
+	set_ioapic_id(VIO_APIC_VADDR, 0x02);
 
 	/* affirm full set of redirection table entries ("write once") */
-	reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
+	reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
 
 	/* PCH-LP has 39 redirection entries */
 	reg32 &= ~0x00ff0000;
 	reg32 |= 0x00270000;
 
-	io_apic_write(IO_APIC_ADDR, 0x01, reg32);
+	io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
 
 	/*
 	 * Select Boot Configuration register (0x03) and
 	 * use Processor System Bus (0x01) to deliver interrupts.
 	 */
-	io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
+	io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
 }
 
 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index de043f4dea..fd28cfe5e6 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = {
 static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
 
 /* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u8 *mei_base_address;
 void intel_me_mbp_clear(device_t dev);
 
 #if CONFIG_DEBUG_INTEL_ME
@@ -572,7 +572,7 @@ void intel_me_finalize(void)
 	u32 reg32;
 
 	/* S3 path will have hidden this device already */
-	if (!mei_base_address || mei_base_address == 0xfffffff0)
+	if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0)
 		return;
 
 #if CONFIG_ME_MBP_CLEAR_LATE
@@ -710,7 +710,7 @@ static int intel_mei_setup(device_t dev)
 		printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
 		return -1;
 	}
-	mei_base_address = res->base;
+	mei_base_address = res2mmio(res, 0, 0);
 
 	/* Ensure Memory and Bus Master bits are set */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index 43aeec20ae..6fd8e63652 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -68,7 +68,7 @@ static const u32 minihd_verb_table[] = {
 static void minihd_init(struct device *dev)
 {
 	struct resource *res;
-	u32 base, reg32;
+	u8 *base, reg32;
 	int codec_mask, i;
 
 	/* Find base address */
@@ -76,8 +76,8 @@ static void minihd_init(struct device *dev)
 	if (!res)
 		return;
 
-	base = (u32)res->base;
-	printk(BIOS_DEBUG, "Mini-HD: base = %08x\n", (u32)base);
+	base = res2mmio(res, 0, 0);
+	printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
 
 	/* Set Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index e8d1fbe684..13b4fe09bf 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -45,7 +45,8 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
 static void sata_init(struct device *dev)
 {
 	config_t *config = dev->chip_info;
-	u32 reg32, abar;
+	u32 reg32;
+	u8 *abar;
 	u16 reg16;
 
 	printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
@@ -107,8 +108,8 @@ static void sata_init(struct device *dev)
 	pci_write_config32(dev, 0x94, reg32);
 
 	/* Initialize AHCI memory-mapped space */
-	abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
-	printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+	abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5));
+	printk(BIOS_DEBUG, "ABAR: %p\n", abar);
 
 	/* CAP (HBA Capabilities) : enable power management */
 	reg32 = read32(abar + 0x00);
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index e2b17afa66..82f37cdb94 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -37,9 +37,9 @@
 /* Set D3Hot Power State in ACPI mode */
 static void serialio_enable_d3hot(struct resource *res)
 {
-	u32 reg32 = read32(res->base + PCH_PCS);
+	u32 reg32 = read32(res2mmio(res, PCH_PCS, 0));
 	reg32 |= PCH_PCS_PS_D3HOT;
-	write32(res->base + PCH_PCS, reg32);
+	write32(res2mmio(res, PCH_PCS, 0), reg32);
 }
 
 static int serialio_uart_is_debug(struct device *dev)
@@ -58,9 +58,9 @@ static int serialio_uart_is_debug(struct device *dev)
 /* Enable clock in PCI mode */
 static void serialio_enable_clock(struct resource *bar0)
 {
-	u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK);
+	u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
 	reg32 |= SIO_REG_PPR_CLOCK_EN;
-	write32(bar0->base + SIO_REG_PPR_CLOCK, reg32);
+	write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
 }
 
 /* Put Serial IO D21:F0-F6 device into desired mode. */
@@ -111,22 +111,22 @@ static void serialio_d21_ltr(struct resource *bar0)
 	u32 reg;
 
 	/* 1. Program BAR0 + 808h[2] = 0b */
-	reg = read32(bar0->base + SIO_REG_PPR_GEN);
+	reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
 	reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
-	write32(bar0->base + SIO_REG_PPR_GEN, reg);
+	write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
 
 	/* 2. Program BAR0 + 804h[1:0] = 00b */
-	reg = read32(bar0->base + SIO_REG_PPR_RST);
+	reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
 	reg &= ~SIO_REG_PPR_RST_ASSERT;
-	write32(bar0->base + SIO_REG_PPR_RST, reg);
+	write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
 
 	/* 3. Program BAR0 + 804h[1:0] = 11b */
-	reg = read32(bar0->base + SIO_REG_PPR_RST);
+	reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
 	reg |= SIO_REG_PPR_RST_ASSERT;
-	write32(bar0->base + SIO_REG_PPR_RST, reg);
+	write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
 
 	/* 4. Program BAR0 + 814h[31:0] = 00000000h */
-	write32(bar0->base + SIO_REG_AUTO_LTR, 0);
+	write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
 }
 
 /* Enable LTR Auto Mode for D23:F0. */
@@ -135,26 +135,26 @@ static void serialio_d23_ltr(struct resource *bar0)
 	u32 reg;
 
 	/* Program BAR0 + 1008h[2] = 1b */
-	reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN);
+	reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
 	reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
-	write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg);
+	write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
 
 	/* Program BAR0 + 1010h = 0x00000000 */
-	write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0);
+	write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
 
 	/* Program BAR0 + 3Ch[30] = 1b */
-	reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12);
+	reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
 	reg |= SIO_REG_SDIO_PPR_CMD12_B30;
-	write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg);
+	write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
 }
 
 /* Select I2C voltage of 1.8V or 3.3V. */
 static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
 {
-	u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN);
+	u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
 	reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
 	reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
-	write32(bar0->base + SIO_REG_PPR_GEN, reg32);
+	write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
 }
 
 /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index eeffda0378..4710271070 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -168,7 +168,7 @@ enum {
 
 static u8 readb_(const void *addr)
 {
-	u8 v = read8((unsigned long)addr);
+	u8 v = read8(addr);
 	printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
 	       v, ((unsigned) addr & 0xffff) - 0xf020);
 	return v;
@@ -176,7 +176,7 @@ static u8 readb_(const void *addr)
 
 static u16 readw_(const void *addr)
 {
-	u16 v = read16((unsigned long)addr);
+	u16 v = read16(addr);
 	printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
 	       v, ((unsigned) addr & 0xffff) - 0xf020);
 	return v;
@@ -184,7 +184,7 @@ static u16 readw_(const void *addr)
 
 static u32 readl_(const void *addr)
 {
-	u32 v = read32((unsigned long)addr);
+	u32 v = read32(addr);
 	printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
 	       v, ((unsigned) addr & 0xffff) - 0xf020);
 	return v;
@@ -192,33 +192,33 @@ static u32 readl_(const void *addr)
 
 static void writeb_(u8 b, const void *addr)
 {
-	write8((unsigned long)addr, b);
+	write8(addr, b);
 	printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
 	       b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 static void writew_(u16 b, const void *addr)
 {
-	write16((unsigned long)addr, b);
+	write16(addr, b);
 	printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
 	       b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 static void writel_(u32 b, const void *addr)
 {
-	write32((unsigned long)addr, b);
+	write32(addr, b);
 	printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
 	       b, ((unsigned) addr & 0xffff) - 0xf020);
 }
 
 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
 
-#define readb_(a) read8((uint32_t)a)
-#define readw_(a) read16((uint32_t)a)
-#define readl_(a) read32((uint32_t)a)
-#define writeb_(val, addr) write8((uint32_t)addr, val)
-#define writew_(val, addr) write16((uint32_t)addr, val)
-#define writel_(val, addr) write32((uint32_t)addr, val)
+#define readb_(a) read8(a)
+#define readw_(a) read16(a)
+#define readl_(a) read32(a)
+#define writeb_(val, addr) write8(addr, val)
+#define writew_(val, addr) write16(addr, val)
+#define writel_(val, addr) write32(addr, val)
 
 #endif  /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
 
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index 89e1139f14..60223c1310 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -27,7 +27,7 @@
 #include <broadwell/xhci.h>
 
 #ifdef __SMM__
-static u32 usb_xhci_mem_base(device_t dev)
+static u8 *usb_xhci_mem_base(device_t dev)
 {
 	u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
@@ -35,7 +35,7 @@ static u32 usb_xhci_mem_base(device_t dev)
 	if (mem_base == 0 || mem_base == 0xffffffff)
 		return 0;
 
-	return mem_base & ~0xf;
+	return (u8 *)(mem_base & ~0xf);
 }
 
 static int usb_xhci_port_count_usb3(device_t dev)
@@ -44,9 +44,9 @@ static int usb_xhci_port_count_usb3(device_t dev)
 	return 4;
 }
 
-static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
 {
-	u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+	u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
 	u32 status = read32(portsc);
 	/* Do not set Port Enabled/Disabled field */
 	status &= ~XHCI_USB3_PORTSC_PED;
@@ -55,9 +55,9 @@ static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
 	write32(portsc, status);
 }
 
-static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
+static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
 {
-	u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+	u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
 	write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
 }
 
@@ -76,7 +76,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
 	u32 status, port_disabled;
 	int timeout, port;
 	int port_count = usb_xhci_port_count_usb3(dev);
-	u32 mem_base = usb_xhci_mem_base(dev);
+	u8 *mem_base = usb_xhci_mem_base(dev);
 
 	if (!mem_base || !port_count)
 		return;
@@ -105,7 +105,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
 
 	/* Reset all requested ports */
 	for (port = 0; port < port_count; port++) {
-		u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
+		u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
 		/* Skip disabled ports */
 		if (port_disabled & (1 << port))
 			continue;
@@ -146,7 +146,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
 {
 	u16 reg16;
 	u32 reg32;
-	u32 mem_base = usb_xhci_mem_base(dev);
+	u8 *mem_base = usb_xhci_mem_base(dev);
 
 	if (!mem_base || slp_typ < 3)
 		return;