intel: Use CF9 reset (part 1)

Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.

Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

6 files changed, 4 insertions, 73 deletions

diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index ffd7c7311f..066f1bed48 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -20,7 +20,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select HAVE_MONOTONIC_TIMER
 	select HAVE_SMI_HANDLER
-	select HAVE_HARD_RESET
+	select SOUTHBRIDGE_INTEL_COMMON_RESET
 	select HAVE_USBDEBUG
 	select IOAPIC
 	select REG_SCRIPT
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index c4f45388f8..4e4d3ebe55 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -43,8 +43,6 @@ romstage-y += pmutil.c
 smm-y      += pmutil.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
-ramstage-y += reset.c
-romstage-y += reset.c
 ramstage-y += sata.c
 ramstage-y += serialio.c
 ramstage-y += smbus.c
diff --git a/src/soc/intel/broadwell/include/soc/reset.h b/src/soc/intel/broadwell/include/soc/reset.h
deleted file mode 100644
index 4edb598ae2..0000000000
--- a/src/soc/intel/broadwell/include/soc/reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _BROADWELL_RESET_H_
-#define _BROADWELL_RESET_H_
-
-void reset_system(void);
-
-#endif
diff --git a/src/soc/intel/broadwell/reset.c b/src/soc/intel/broadwell/reset.c
deleted file mode 100644
index ad90dcd880..0000000000
--- a/src/soc/intel/broadwell/reset.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <halt.h>
-#include <reset.h>
-#include <soc/reset.h>
-
-/*
- * Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
- * Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
- * Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
- * Warm reset (PLTRST# assertion) - write 0x6 to I/O 0xcf9
- * Global reset (S0->S5->S0 with ME reset) - write 0x6 or 0xe to 0xcf9 but
- * with ETR[20] set.
- */
-
-void do_soft_reset(void)
-{
-	outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
-	outb(0x06, 0xcf9);
-}
-
-void reset_system(void)
-{
-	hard_reset();
-	halt();
-}
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 54db3d1564..c4a3b2c9d9 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -18,6 +18,7 @@
 #include <assert.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <lib.h>
@@ -33,7 +34,6 @@
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 #include <soc/pm.h>
-#include <soc/reset.h>
 #include <soc/romstage.h>
 #include <soc/smm.h>
 #include <soc/systemagent.h>
@@ -63,7 +63,7 @@ void raminit(struct pei_data *pei_data)
 		/* Waking from S3 and no cache. */
 		printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
 		post_code(POST_RESUME_FAILURE);
-		reset_system();
+		system_reset();
 	} else {
 		printk(BIOS_DEBUG, "No MRC cache found.\n");
 	}
@@ -108,7 +108,7 @@ void raminit(struct pei_data *pei_data)
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 		printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
 		/* Failed S3 resume, reset to come up cleanly */
-		reset_system();
+		system_reset();
 #endif
 	}
 
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index a6691ab9f9..3abc853975 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -32,7 +32,6 @@
 #include <soc/me.h>
 #include <soc/pei_data.h>
 #include <soc/pm.h>
-#include <soc/reset.h>
 #include <soc/romstage.h>
 #include <soc/spi.h>