summaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell
diff options
context:
space:
mode:
authorLee Leahy <leroy.p.leahy@intel.com>2014-11-20 16:56:44 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-04 12:40:30 +0200
commit4a69c34d54d587ba00c6c8e4f9056596014a7541 (patch)
tree999e9f145ca9d35c50e8bcd2823b673c5ec4bc3d /src/soc/intel/broadwell
parent9f5a5c532343fe72753fc507b0f2ef1a26afabd3 (diff)
Broadwell: Pass TSC value to romstage_main
The romstage_main routine takes three parameters: bist, tsc_low and tsc_hi. However in cache_as_ram.inc only the bist value is being passed. This patch adds the two halves of the TSC value. BRANCH=none BUG=None TEST=Build and run on Samus Change-Id: I3d216edd0be65f29b51a66ed67b2d17910a594d4 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: de565f28dce8a549d74defbcf5eaf8116bb1b831 Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Original-Change-Id: I34fb21e493dcb3a44426ba7964cd72a319a4254e Original-Reviewed-on: https://chromium-review.googlesource.com/231173 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9280 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell')
-rw-r--r--src/soc/intel/broadwell/romstage/cache_as_ram.inc6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 4e6cf09f72..a10ca4ca1b 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -180,7 +180,13 @@ clear_mtrrs:
/* Restore the BIST result. */
movl %ebp, %eax
+
+ /* Build the call frame. */
movl %esp, %ebp
+ movd %mm1, %ebx
+ pushl %ebx
+ movd %mm0, %ebx
+ pushl %ebx
pushl %eax
before_romstage: