diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-26 14:03:31 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-08 19:16:24 +0100 |
| commit | 2bad1e7f491ea9347899498d7d8dde4e1dd9b6d4 (patch) | |
| tree | 7a1273925b7401e9d4fbe019cda72faea0494de5 /src/soc/intel/broadwell | |
| parent | 76679d1e963824aade23b7b8fec69c6a1eed4a08 (diff) | |
intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE
Not referenced in code.
Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17268
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/Kconfig | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 517fd21ee8..29b5bfe6fa 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -106,13 +106,6 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. -config DCACHE_RAM_ROMSTAGE_STACK_SIZE - hex - default 0x2000 - help - The amount of anticipated stack usage from the data cache - during pre-ram ROM stage execution. - config HAVE_MRC bool "Add a Memory Reference Code binary" help |