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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-31 16:10:05 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-16 04:18:36 +0000 |
| commit | 3838edeac672a7f61597e6d38e14c16a84329d60 (patch) | |
| tree | 8ca0f437e57a43d88375f9d5da5e5226c590d89e /src/soc/intel/broadwell | |
| parent | 8a18bd8500fee7c43e257d3dfd1cc3f7db82c88c (diff) | |
soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
Move locking CPU MSRs during CPU init instead of using
CONFIG_PARALLEL_MP_AP_WORK functions.
The AES Lock enable bit caused CPU exception errors as this should not
run on HT siblings. The set_aesni_lock() function takes care of that.
Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55098
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell')
0 files changed, 0 insertions, 0 deletions