diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-02 08:44:47 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-05 01:38:15 +0000 |
| commit | 4e6b7907de07c9c7d4b01a6213a8e13e946398cb (patch) | |
| tree | d6cb8f208a588506710e36a38d141d9228af7483 /src/soc/intel/broadwell | |
| parent | 19c0ae540ea992b76eb65421381269def0a6328d (diff) | |
src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/msr.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index ee1fd528cc..3ef0d722b6 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -394,7 +394,7 @@ static void configure_c_states(void) { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 31); // Timed MWAIT Enable msr.lo |= (1 << 30); // Package c-state Undemotion Enable msr.lo |= (1 << 29); // Package c-state Demotion Enable @@ -404,7 +404,7 @@ static void configure_c_states(void) msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 41ce17c10b..c2a939e392 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -23,7 +23,7 @@ #define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c #define SMM_MCA_CAP_MSR 0x17d |