diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-23 13:28:57 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-24 12:04:25 +0000 |
| commit | e751a101c08d540c59fc39def9681a0ee227d825 (patch) | |
| tree | 89443ef7d6e3f5d8318dd5b8b9ff35834fc1bc91 /src/soc/intel/broadwell | |
| parent | b89c8bb13536abeb84bfaad28bbbd8ebfacb0137 (diff) | |
soc/intel/broadwell: Move romstage.c to Haswell
Broadwell no longer has CPU code.
Change-Id: I9c9717439a702dddaa613a30e6f3da29887ec4bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46951
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell')
| -rw-r--r-- | src/soc/intel/broadwell/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/cpu/romstage.c | 30 |
2 files changed, 0 insertions, 32 deletions
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index dc16ae4bb9..5e0ce649bf 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,7 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -romstage-y += cpu/romstage.c - subdirs-y += pch bootblock-y += bootblock.c diff --git a/src/soc/intel/broadwell/cpu/romstage.c b/src/soc/intel/broadwell/cpu/romstage.c deleted file mode 100644 index 3b11e93cab..0000000000 --- a/src/soc/intel/broadwell/cpu/romstage.c +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/cpu.h> -#include <console/console.h> -#include <cpu/intel/haswell/haswell.h> -#include <cpu/x86/msr.h> - -void set_max_freq(void) -{ - msr_t msr, perf_ctl, platform_info; - - /* Check for configurable TDP option */ - platform_info = rdmsr(MSR_PLATFORM_INFO); - - if ((platform_info.hi >> 1) & 3) { - /* Set to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - perf_ctl.lo = (msr.lo & 0xff) << 8; - } else { - /* Platform Info bits 15:8 give max ratio */ - msr = rdmsr(MSR_PLATFORM_INFO); - perf_ctl.lo = msr.lo & 0xff00; - } - - perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); - - printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); -} |