soc/intel/common: add TCC activation functionality

This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value. Also, cleanup local functions
from previous intel soc specific code base like for apollolake, broadwell,
skylake and cannonlake.

BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.

Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 1 insertions, 17 deletions

diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 4bfa15d354..1312525814 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -290,22 +290,6 @@ static void configure_c_states(void)
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
 }
 
-static void configure_thermal_target(void)
-{
-	config_t *conf = config_of_soc();
-	msr_t msr;
-
-
-	/* Set TCC activation offset if supported */
-	msr = rdmsr(MSR_PLATFORM_INFO);
-	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
-		msr = rdmsr(MSR_TEMPERATURE_TARGET);
-		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
-		msr.lo |= (conf->tcc_offset & 0xf) << 24;
-		wrmsr(MSR_TEMPERATURE_TARGET, msr);
-	}
-}
-
 static void configure_misc(void)
 {
 	msr_t msr;
@@ -430,7 +414,7 @@ static void cpu_core_init(struct device *cpu)
 	configure_misc();
 
 	/* Thermal throttle activation offset */
-	configure_thermal_target();
+	configure_tcc_thermal_target();
 
 	/* Enable Direct Cache Access */
 	configure_dca_cap();