diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 21:37:21 +0200 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 00:45:51 +0000 |
commit | c200e8c7cdebed98860a771888efbf998c5912b3 (patch) | |
tree | 2a3d0151583646b33a5ba6e518c23e403433be85 /src/soc/intel/broadwell/smi.c | |
parent | 3cc2c38d50741fffb9193851a4a3b7c636f7cd4d (diff) |
soc/intel/broadwell: Move PCH code into pch subdir
Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46706
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/smi.c')
-rw-r--r-- | src/soc/intel/broadwell/smi.c | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c deleted file mode 100644 index d7704fd8fa..0000000000 --- a/src/soc/intel/broadwell/smi.c +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> -#include <arch/io.h> -#include <cpu/x86/smm.h> -#include <cpu/intel/smm_reloc.h> -#include <soc/iomap.h> -#include <soc/pch.h> -#include <soc/pm.h> - -void smm_southbridge_clear_state(void) -{ - u32 smi_en; - - printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS); - - smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); - if (smi_en & APMC_EN) { - printk(BIOS_INFO, "SMI# handler already enabled?\n"); - return; - } - - printk(BIOS_DEBUG, "\n"); - - /* Dump and clear status registers */ - clear_smi_status(); - clear_pm1_status(); - clear_tco_status(); - clear_gpe_status(); -} - -static void smm_southbridge_enable(uint16_t pm1_events) -{ - printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events */ - enable_pm1(pm1_events); - disable_gpe(PME_B0_EN); - - /* Enable SMI generation: - * - on APMC writes (io 0xb2) - * - on writes to SLP_EN (sleep states) - * - on writes to GBL_RLS (bios commands) - * No SMIs: - * - on microcontroller writes (io 0x62/0x66) - * - on TCO events - */ - enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); -} - -void global_smi_enable(void) -{ - smm_southbridge_enable(PWRBTN_EN | GBL_EN); -} |