diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-01-06 13:32:42 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-10 20:08:48 +0200 |
| commit | b63d34102ad074d0db2347ffadd30bc6ab834160 (patch) | |
| tree | edf35d12c3f0178f2d20aeeec89131ac235ec2f8 /src/soc/intel/broadwell/sata.c | |
| parent | 88bbf166bc1856156b5b2f3f4767f9365dfd60c6 (diff) | |
broadwell: Update SATA Gen3 TX adjustment registers
The registers that were used here are for CPT/PPT and not
for HSW/BDW chips.
Update this to update just the Gen3 TX Output Voltage Downscale
Amplitude Adjustment field in the SATA ECR T88.
BUG=chrome-os-partner:28234
BRANCH=samus,auron
TEST=build and boot on samus
Change-Id: I94b702dc4a3c98678ba048ff9cfa4a85cc5b1eed
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 4c5816cc647b84266751e8a591eb85d7735fee12
Original-Change-Id: I98ec9678938a6675828721d5b57683077f555d21
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238800
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9484
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/sata.c')
| -rw-r--r-- | src/soc/intel/broadwell/sata.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index cfb3854831..fd1e9f156a 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -138,12 +138,20 @@ static void sata_init(struct device *dev) /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) - pch_iobp_update(SATA_IOBP_SP0G3IR, 0, - config->sata_port0_gen3_tx); + pch_iobp_update(SATA_IOBP_SP0_SECRT88, + ~(SATA_SECRT88_VADJ_MASK << + SATA_SECRT88_VADJ_SHIFT), + (config->sata_port0_gen3_tx & + SATA_SECRT88_VADJ_MASK) + << SATA_SECRT88_VADJ_SHIFT); if (config->sata_port1_gen3_tx) - pch_iobp_update(SATA_IOBP_SP1G3IR, 0, - config->sata_port1_gen3_tx); + pch_iobp_update(SATA_IOBP_SP1_SECRT88, + ~(SATA_SECRT88_VADJ_MASK << + SATA_SECRT88_VADJ_SHIFT), + (config->sata_port1_gen3_tx & + SATA_SECRT88_VADJ_MASK) + << SATA_SECRT88_VADJ_SHIFT); /* Set Gen3 DTLE DATA / EDGE registers if needed */ if (config->sata_port0_gen3_dtle) { |