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authorAaron Durbin <adurbin@chromium.org>2015-03-06 23:17:33 -0600
committerAaron Durbin <adurbin@chromium.org>2015-04-22 17:55:08 +0200
commitbd74a4b2d25268f7035a4478da31f27baac2aecc (patch)
tree56740c02fe396df8ccf9fc2e7401542deeebf453 /src/soc/intel/broadwell/romstage
parentcac50506238507328b8ea0f4abd458869803e6c2 (diff)
coreboot: common stage cache
Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/broadwell/romstage')
-rw-r--r--src/soc/intel/broadwell/romstage/raminit.c13
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c5
2 files changed, 12 insertions, 6 deletions
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index 1f62fd0c8c..52ea49100d 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -29,6 +29,7 @@
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#endif
+#include <stage_cache.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/intel/common/mrc_cache.h>
#include <soc/iomap.h>
@@ -111,12 +112,16 @@ void raminit(struct pei_data *pei_data)
if (pei_data->boot_mode != SLEEP_STATE_S3) {
cbmem_initialize_empty();
- } else if (cbmem_initialize()) {
+ stage_cache_create_empty();
+ } else {
+ stage_cache_recover();
+ if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
- /* Failed S3 resume, reset to come up cleanly */
- reset_system();
+ printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ reset_system();
#endif
+ }
}
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index bf9e2ed3e9..1741ae6b82 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -25,11 +25,12 @@
#include <arch/stages.h>
#include <arch/early_variables.h>
#include <console/console.h>
+#include <cbfs.h>
#include <cbmem.h>
#include <cpu/x86/mtrr.h>
#include <elog.h>
-#include <ramstage_cache.h>
#include <romstage_handoff.h>
+#include <stage_cache.h>
#include <timestamp.h>
#include <soc/me.h>
#include <soc/pei_data.h>
@@ -142,7 +143,7 @@ void asmlinkage romstage_after_car(void)
while (1);
}
-void ramstage_cache_invalid(struct ramstage_cache *cache)
+void ramstage_cache_invalid(void)
{
#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
/* Perform cold reset on invalid ramstage cache. */