broadwell: Preparations for building

Updated Intel Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.

- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic

Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

3 files changed, 19 insertions, 10 deletions

diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
index 029ab7caf4..4e6cf09f72 100644
--- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc
+++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc
@@ -19,7 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c
index d4ebc08da8..7217bb9539 100644
--- a/src/soc/intel/broadwell/romstage/raminit.c
+++ b/src/soc/intel/broadwell/romstage/raminit.c
@@ -85,7 +85,7 @@ void raminit(struct pei_data *pei_data)
 
 	/* Determine if mrc.bin is in the cbfs. */
 	entry = (pei_wrapper_entry_t)cbfs_get_file_content(
-		CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab);
+		CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL);
 	if (entry == NULL) {
 		printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");
 		return;
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 1d5ee89d54..4a5a47c35e 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -31,7 +31,6 @@
 #include <ramstage_cache.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <broadwell/me.h>
 #include <broadwell/pei_data.h>
 #include <broadwell/pm.h>
@@ -39,6 +38,20 @@
 #include <broadwell/romstage.h>
 #include <broadwell/spi.h>
 
+static inline uint64_t timestamp_get(void)
+{
+	return rdtscll();
+}
+
+static inline tsc_t ts64_to_tsc(uint64_t ts)
+{
+	tsc_t tsc = {
+		.lo = ts,
+		.hi = ts >> 32,
+	};
+	return tsc;
+}
+
 static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
 {
 	struct romstage_timestamps *rt = &rp->ts;
@@ -129,19 +142,16 @@ void romstage_common(struct romstage_params *params)
 	chromeos_init(params->power_state->prev_sleep_state);
 
 	/* Save timestamp information. */
-	timestamp_init(params->ts.times[0]);
-	timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
-	timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
-	timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
+	timestamp_init(ts64_to_tsc(params->ts.times[0]));
+	timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
+	timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
+	timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
 }
 
 void asmlinkage romstage_after_car(void)
 {
 	timestamp_add_now(TS_END_ROMSTAGE);
 
-	/* Run vboot verification if configured. */
-	vboot_verify_firmware(romstage_handoff_find_or_add());
-
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);