soc/intel/broadwell: Separate PCH in devicetree

Flesh out the PCH configuration into a separate chip. Keep it within the
Broadwell SoC directory for now, to ease moving files around. The boards
were prepared beforehand and the devicetrees require next to no changes.

Tested on out-of-tree Acer Aspire E5-573, still boots.

Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 3 insertions, 3 deletions

diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index d68e17eee2..149dda1ca0 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -12,7 +12,7 @@
 #include <soc/rcba.h>
 #include <soc/romstage.h>
 #include <soc/smbus.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
 
 static void pch_route_interrupts(void)
 {
@@ -52,9 +52,9 @@ static void pch_route_interrupts(void)
 static void pch_enable_lpc(void)
 {
 	/* Lookup device tree in romstage */
-	const config_t *config;
+	const struct device *const dev = pcidev_on_root(0x1f, 0);
 
-	config = config_of_soc();
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);