aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell/romstage/romstage.c
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-12-22 16:59:44 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-15 17:57:33 +0000
commite43972474c0eebc478722f7c371a8c68318f24cf (patch)
tree34abf5f2a18cb350fe4871b4e8509c5da4705d37 /src/soc/intel/broadwell/romstage/romstage.c
parent4d56a0625516ba436903d59d9c0a4a13827d89be (diff)
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables bootblock console by default. Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel/broadwell/romstage/romstage.c')
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 54434a3153..f8571678d8 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -77,13 +77,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* PCH Early Initialization */
pch_early_init();
- /* Call into mainboard pre console init. Needed to enable serial port
- on IT8772 */
- mainboard_pre_console_init();
-
- /* Start console drivers */
- console_init();
-
/* Get power state */
rp.power_state = fill_power_state();
@@ -125,5 +118,3 @@ void mainboard_romstage_entry(unsigned long bist)
mainboard_post_raminit(&rp);
}
-
-void __weak mainboard_pre_console_init(void) {}