diff options
| author | Kenji Chen <kenji.chen@intel.com> | 2014-09-26 03:14:57 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 17:27:48 +0200 |
| commit | e383feb7c8e1b46639c32df9a11fac6cf3d62403 (patch) | |
| tree | a9f78cc9d181b5c20ea608a8080673cdab07c181 /src/soc/intel/broadwell/pcie.c | |
| parent | c373f503dbbfc2a70e91f576fac01f66126556c2 (diff) | |
Broadwell: Synchronize for power management with FRC
Set Root Port 0 PCI CFG Offset 0xE2[5:4] before ASPM configuration.
BUG=chrome-os-partner:31424
TEST=Build an image, and check the procedure and recommended setting
is applied correctly.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I94820787d4ed4a6bf8db8898b7de14467c9d6630
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 24bdea6cd67d5657b94058233cd26130f68c44e4
Original-Change-Id: I98713f615885ac02867942ece2be1cea8ce04ab2
Original-Reviewed-on: https://chromium-review.googlesource.com/219994
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: http://review.coreboot.org/9211
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/pcie.c')
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index b14ad9dea0..fe22bccf63 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -123,6 +123,8 @@ static void pcie_iosf_port_grant_count(device_t dev) static void root_port_init_config(device_t dev) { int rp; + u32 data; + u8 resp, id; if (root_port_is_first(dev)) { rpc.orig_rpfn = RCBA32(RPFN); @@ -170,6 +172,15 @@ static void root_port_init_config(device_t dev) } pcie_update_cfg(dev, 0x418, 0, 0x02000430); + + /* set RP0 PCICFG E2h[5:4] = 11b before configuring ASPM */ + if (root_port_is_first(dev)) { + id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07); + pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp); + data |= (0x30 << 16); + pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp); + } + /* Cache pci device. */ rpc.ports[rp - 1] = dev; } |