diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-08 14:30:07 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2024-04-16 01:45:36 +0000 |
| commit | fd46b497ead843eccfd80124ca8fbba7e57a3631 (patch) | |
| tree | 597063b76d3b640d5d71e40d060a6cd954342dce /src/soc/intel/broadwell/pch | |
| parent | ebba6da073e51569bd962e86bf8162e7b4da9321 (diff) | |
lynxpoint/broadwell: Correct L1 exit latency with ASPM
Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit
latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does
the same. Correct the condition accordingly. On Lynx Point, also remove
a now-redundant write to the LCAP register (offset 0x4c).
Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch')
| -rw-r--r-- | src/soc/intel/broadwell/pch/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 966a25d661..4847da6788 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -522,7 +522,7 @@ static void pch_pcie_early(struct device *dev) pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ - if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) + if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); |