diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-12-28 13:05:56 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-04 11:48:19 +0000 |
| commit | af4bd5633debc8838b563c3fadd96e2b4b060ab5 (patch) | |
| tree | 6867d466f6e3b7ca8e6077979a404caf7609a747 /src/soc/intel/broadwell/pch | |
| parent | 0b9d186e3dc7c209d0fc26b61db3cd98550b71bd (diff) | |
sb/intel: Use `bool` for PCIe coalescing option
Retype the `pcie_port_coalesce` devicetree options and related variables
to better reflect their bivalue (boolean) nature.
Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch')
| -rw-r--r-- | src/soc/intel/broadwell/pch/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pch/pcie.c | 7 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h index 2164a31050..84ad8fe820 100644 --- a/src/soc/intel/broadwell/pch/chip.h +++ b/src/soc/intel/broadwell/pch/chip.h @@ -3,7 +3,7 @@ #ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_ #define _SOC_INTEL_BROADWELL_PCH_CHIP_H_ -#include <stdint.h> +#include <types.h> struct soc_intel_broadwell_pch_config { /* GPE configuration */ @@ -47,7 +47,7 @@ struct soc_intel_broadwell_pch_config { uint32_t gen4_dec; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; /* Force root port ASPM configuration with port bitmap */ uint8_t pcie_port_force_aspm; diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 29915d6e13..5997768730 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <cpu/intel/haswell/haswell.h> +#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> @@ -15,7 +16,7 @@ #include <soc/intel/broadwell/pch/chip.h> #include <southbridge/intel/lynxpoint/iobp.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <delay.h> +#include <types.h> /* Low Power variant has 6 root ports. */ #define MAX_NUM_ROOT_PORTS 6 @@ -31,7 +32,7 @@ struct root_port_config { u32 b0d28f0_32c; u32 b0d28f4_32c; u32 b0d28f5_32c; - int coalesce; + bool coalesce; int gbe_port; int num_ports; struct device *ports[MAX_NUM_ROOT_PORTS]; @@ -274,7 +275,7 @@ static void root_port_commit_config(void) /* If the first root port is disabled the coalesce ports. */ if (!rpc.ports[0]->enabled) - rpc.coalesce = 1; + rpc.coalesce = true; /* Perform clock gating configuration. */ pcie_enable_clock_gating(); |