soc/intel/broadwell/pch: Prepare to drop `gpio.h`

Use `lp_gpio.h` from Lynxpoint instead. Subsequent commits will update
the mainboards and then drop all GPIO code from Broadwell.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: Idef89037c2ca781ac3e921abb4b3dc3f7c4b3b5f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50079
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 6 insertions, 4 deletions

diff --git a/src/soc/intel/broadwell/pch/gpio.c b/src/soc/intel/broadwell/pch/gpio.c
index 952329117e..a1c8345d3b 100644
--- a/src/soc/intel/broadwell/pch/gpio.c
+++ b/src/soc/intel/broadwell/pch/gpio.c
@@ -4,9 +4,9 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 /*
  * This function will return a number that indicates which PIRQ
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 873e57e12a..377a4da77a 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -13,7 +13,6 @@
 #include <acpi/acpi_gnvs.h>
 #include <cpu/x86/smm.h>
 #include <string.h>
-#include <soc/gpio.h>
 #include <soc/iobp.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
@@ -26,6 +25,7 @@
 #include <soc/intel/broadwell/pch/chip.h>
 #include <acpi/acpigen.h>
 #include <southbridge/intel/common/rtc.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 static void pch_enable_ioapic(struct device *dev)
 {
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c
index 141fc14168..7f16cb4d2c 100644
--- a/src/soc/intel/broadwell/pch/pcie.c
+++ b/src/soc/intel/broadwell/pch/pcie.c
@@ -8,13 +8,13 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <soc/gpio.h>
 #include <soc/lpc.h>
 #include <soc/iobp.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/rcba.h>
 #include <soc/intel/broadwell/pch/chip.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <delay.h>
 
 /* Low Power variant has 6 root ports. */
diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c
index be383277e5..59ae72f3fc 100644
--- a/src/soc/intel/broadwell/pch/pmutil.c
+++ b/src/soc/intel/broadwell/pch/pmutil.c
@@ -17,10 +17,12 @@
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
-#include <soc/gpio.h>
 #include <security/vboot/vbnv.h>
 #include <stdint.h>
 
+#define GPIO_ALT_GPI_SMI_STS	0x50
+#define GPIO_ALT_GPI_SMI_EN	0x54
+
 static inline uint16_t get_gpiobase(void)
 {
 	return GPIO_BASE_ADDRESS;