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authorAngel Pons <th3fanbus@gmail.com>2020-10-23 21:37:21 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-10-30 00:45:51 +0000
commitc200e8c7cdebed98860a771888efbf998c5912b3 (patch)
tree2a3d0151583646b33a5ba6e518c23e403433be85 /src/soc/intel/broadwell/pch/usb_debug.c
parent3cc2c38d50741fffb9193851a4a3b7c636f7cd4d (diff)
soc/intel/broadwell: Move PCH code into pch subdir
Change-Id: Icb57eb89b4f225298e43ae27970dc1e27fb6e222 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46706 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch/usb_debug.c')
-rw-r--r--src/soc/intel/broadwell/pch/usb_debug.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/pch/usb_debug.c b/src/soc/intel/broadwell/pch/usb_debug.c
new file mode 100644
index 0000000000..0fda336d14
--- /dev/null
+++ b/src/soc/intel/broadwell/pch/usb_debug.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <device/pci_ehci.h>
+#include <device/pci_def.h>
+
+pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
+{
+ return PCI_DEV(0, 0x1d, 0);
+}
+
+void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
+{
+ /* Hardcoded to physical port 1 */
+}