diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-23 13:15:19 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-24 12:03:55 +0000 |
| commit | 9d733def594cd9b982260743d2c48b3abad17255 (patch) | |
| tree | 1aa4f16e8e42a4edf5b38a0f9d117bb4d32920be /src/soc/intel/broadwell/pch/pcie.c | |
| parent | 739a6ad1ac098231c34587c69237906e721b7e91 (diff) | |
soc/intel/broadwell: Use Haswell CPU headers
Now that the boards use Haswell's CPU code, Broadwell can be updated.
Change-Id: If07e5272f07edb59bb18eef1f80d7d5807b26e66
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46949
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch/pcie.c')
| -rw-r--r-- | src/soc/intel/broadwell/pch/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index c98201e5ab..b098dc2af4 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> @@ -14,7 +15,6 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/intel/broadwell/pch/chip.h> -#include <soc/cpu.h> #include <delay.h> /* Low Power variant has 6 root ports. */ |