diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-15 05:58:42 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-16 09:28:42 +0000 |
| commit | 4de1a31cb04f0363b6d257d9de392cdfe8d5644c (patch) | |
| tree | 80a674e5d82d33c5e133d31676ab48bad409798e /src/soc/intel/broadwell/pch/lpc.c | |
| parent | cdd2f63947549e9b478f26942daf400cf4f246e6 (diff) | |
ACPI: Add acpi_reset_gnvs_for_wake()
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch/lpc.c')
| -rw-r--r-- | src/soc/intel/broadwell/pch/lpc.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 377a4da77a..e6900d69c1 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -10,13 +10,11 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <string.h> #include <soc/iobp.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/nvs.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -603,12 +601,6 @@ static void pch_lpc_read_resources(struct device *dev) pch_lpc_add_io_resources(dev); } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - /* Set unknown wake source */ - gnvs->pm1i = -1; -} - static unsigned long broadwell_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) |