diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-12 17:46:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-27 10:25:03 +0000 |
| commit | 4abc73183134def757c553aa4eb195fffa824100 (patch) | |
| tree | e6fa253f8e7dc46e80a0a33ea903b4fe0be83419 /src/soc/intel/broadwell/pch/acpi | |
| parent | aeffa86cc551110b62074fa6302f4960d87a9a8c (diff) | |
ACPI: Separate device_nvs_t
Remove typedef device_nvs_t and move struct device_nvs
outside of global_nvs. Also remove padding and the reserve
for chromeos_acpi_t.
Change-Id: I878746b1f0f9152a27dc58e373d58115e2dff22c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch/acpi')
| -rw-r--r-- | src/soc/intel/broadwell/pch/acpi/globalnvs.asl | 36 |
1 files changed, 1 insertions, 35 deletions
diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index b83b957c6c..88fe4b1218 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -12,7 +12,7 @@ Name (\PICM, 0) // IOAPIC/8259 */ External (NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -47,40 +47,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - - Offset (0x1000), - /* Device enables in ACPI mode */ - S0EN, 8, // DMA Enable - S1EN, 8, // I2C0 Enable - S2EN, 8, // I2C1 Enable - S3EN, 8, // SPI0 Enable - S4EN, 8, // SPI1 Enable - S5EN, 8, // UART0 Enable - S6EN, 8, // UART1 Enable - S7EN, 8, // SDIO Enable - S8EN, 8, // ADSP Enable - - /* BAR 0 */ - S0B0, 32, // DMA BAR0 - S1B0, 32, // I2C0 BAR0 - S2B0, 32, // I2C1 BAR0 - S3B0, 32, // SPI0 BAR0 - S4B0, 32, // SPI1 BAR0 - S5B0, 32, // UART0 BAR0 - S6B0, 32, // UART1 BAR0 - S7B0, 32, // SDIO BAR0 - S8B0, 32, // ADSP BAR0 - - /* BAR 1 */ - S0B1, 32, // DMA BAR1 - S1B1, 32, // I2C0 BAR1 - S2B1, 32, // I2C1 BAR1 - S3B1, 32, // SPI0 BAR1 - S4B1, 32, // SPI1 BAR1 - S5B1, 32, // UART0 BAR1 - S6B1, 32, // UART1 BAR1 - S7B1, 32, // SDIO BAR1 - S8B1, 32, // ADSP BAR1 } /* Set flag to enable USB charging in S3 */ |