diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2017-10-17 16:52:43 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-01 20:02:02 +0000 |
| commit | 154cd41037c6298faa94d046e8582f0674031dca (patch) | |
| tree | 8d25522ad4c24b77cf1280127917285172558800 /src/soc/intel/broadwell/pch.c | |
| parent | 9a506d5c9ae60a368df924d70cd1bbae303f3a9e (diff) | |
intel/cannonlake_rvp: enable CNVi wifi
Leaving the wifi related gpios unmodified for now
due to FSP problem. If H0-H3 is configured as native mode
and GPIORXDIS, GPIOTXDIS bits in DW0 are cleared, it causes
FSP to assert when wifi module is attached. coreboot gpio
macros clears these 2 bits because they are suppose to be
"don't care" in native mode.
TEST=Boot to OS and verify wifi
Change-Id: Ica5e1c43802d04a9471cdfa0087e86f669122fff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/broadwell/pch.c')
0 files changed, 0 insertions, 0 deletions