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authorElyes HAOUAS <ehaouas@noos.fr>2020-04-29 10:42:34 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-01 16:35:06 +0000
commitb887adf7a56f2877c41e808002f30841a6679eb6 (patch)
tree21610d86c82b79f9c72e89b4be09fac4035d2505 /src/soc/intel/broadwell/minihd.c
parent3e42ee05d86c1de3ed23dddf08fd8e6451bdea92 (diff)
soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/minihd.c')
-rw-r--r--src/soc/intel/broadwell/minihd.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c
index 2dcab97ae9..da0b42a47e 100644
--- a/src/soc/intel/broadwell/minihd.c
+++ b/src/soc/intel/broadwell/minihd.c
@@ -62,8 +62,7 @@ static void minihd_init(struct device *dev)
printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Mini-HD configuration */
reg32 = read32(base + 0x100c);